A Digital-to-Time Converter (DTC) commonly comprises a Multi-Modulus Divider (MMD) providing a coarse phase modulation and Digitally-Controlled Edge Interpolator (DCEI) providing the fine modulation. Current DCEI architectures have several challenges. For example, the current consumption of the DCEI is code-dependent so that dynamic errors rise in the presence of finite load regulation (as it is the case for Low-DropOut, LDO, regulators). Moreover, dynamic errors occur when the coarse modulation by the MMD changes. Also, there is a trade-off between static Integral Non-Linearity (INL), power dissipation and phase noise.
Hence, there may be a desire for an improved phase interpolation architecture.